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[Other resource] USB 2.0 IP Core

Description: USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
Platform: | Size: 181283 | Author: 林风 | Hits:

[Other resource] USB 1.1 IP-CORE和设计范例 VHDL源代码

Description: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Platform: | Size: 426278 | Author: ken | Hits:

[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码

Description: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Platform: | Size: 425984 | Author: ken | Hits:

[VHDL-FPGA-Verilog] usb1.1_Verilog

Description: usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
Platform: | Size: 131072 | Author: 李恒 | Hits:

[USB develop] usb_doc

Description: USB IP core.very good
Platform: | Size: 142336 | Author: 张卫 | Hits:

[VHDL-FPGA-Verilog] USB IPcore（带说明）

Description: USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
Platform: | Size: 408576 | Author: 陈友荣 | Hits:

[VHDL-FPGA-Verilog] USB 2.0 IP Core

Description: USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
Platform: | Size: 181248 | Author: 林风 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Platform: | Size: 206848 | Author: 张清平 | Hits:

[Other Embeded program] usb11_test

Description: 该范例使用FreeDev_usb11 ip core支持开发板成为USB HOST的 设备（常见的是PC机）。
Platform: | Size: 59392 | Author: HuFengzhang | Hits:

[Other] free_IP_1

Description: 来自于OpenCores组织的开放IP核，非常专业，大牛编写。-OpenCores organizations from open IP core, very professional, big cattle preparation.
Platform: | Size: 2644992 | Author: wangyunshann | Hits:

[Software Engineering] WNUSB

Description: [UsbKbd.rar] - usbkbd,用wdm编写的usb和键盘的驱动示例 [USB2.0_USB_driver.rar] - 学习USB2.0驱动程序设计源码，包括Windows DDK Driver驱动的详细设计，U盘，MP3的程序设计例子 [mc8051_design.zip] - MC8051 IP CoreOregano Systems 8-bit Microcontroller IP-Core此公司提供的8051 -[UsbKbd.rar]- usbkbd, prepared with wdm drivers usb and keyboard sample [USB2.0_USB_driver.rar]- Learning USB2.0 Driver source, including the Windows DDK Driver drive the detailed design, U disk, MP3
Platform: | Size: 23552 | Author: 王军 | Hits:

[USB develop] usb20_ipcore_usb_funct

Description: usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL description suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
Platform: | Size: 208896 | Author: road | Hits:

[VHDL-FPGA-Verilog] USB

Description: 用VHDL实现的USB IP核，大家可以参考下-Use VHDL to achieve USB IP core, we can refer to the following
Platform: | Size: 1146880 | Author: 蔡飞 | Hits:

[VHDL-FPGA-Verilog] usb11

Description: 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。-Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
Platform: | Size: 414720 | Author: 戴求淼 | Hits:

[USB develop] usb

Description: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Platform: | Size: 6144 | Author: polito | Hits:

[Other] slaveController

Description: 对USB的从机设备的IP核进行了重新设计并在一定程度上进行了优化-On the USB device from the IP core has been redesigned to some extent, is optimized
Platform: | Size: 56320 | Author: shaqiu | Hits:

[VHDL-FPGA-Verilog] usb

Description: USB完整代码 包括vhdl和verilog两种-usb ip core
Platform: | Size: 260096 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] verilog-usb--protel-design

Description: 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
Platform: | Size: 53248 | Author: 唐明桂 | Hits:

[USB develop] USB-1.1-IP-CORE-VHDL

Description: USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
Platform: | Size: 425984 | Author: sxhfjgl010 | Hits:

[Documents] pg137-axi-usb2-device(xilinx USB ip core)

Description: xilinx USB ip 核使用说明文档，接口完全和usb3320接口一致(Xilinx USB IP core usage instructions document, the interface is completely consistent with the usb3320 interface)
Platform: | Size: 716800 | Author: 黄国锋 | Hits:
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